Method of making small transistor lengths

ABSTRACT

Transistor gate linewidths can be made to be effectively smaller by etching a notch at the bottom of the gate to reduce the effective linewidth. This can be done by etching at a layer interface, such as a silicon-germanium interface. in an over-etch step.

METHOD OF MAKING SMALL TRANSISTOR LENGTHS

[0001] This invention relates to a method for forming small linewidthtransistors. More particularly, this invention relates to forming verysmall apparent gate linewidths by etching a notch at the interface of asilicon-germanium stack.

BACKGROUND OF THE INVENTION

[0002] As the effective width of a gate stack becomes smaller, thetransistors that can be made from them become faster. However, withpresent line widths at 0.25 micron, or even 0.18 micron, it isincreasingly difficult to anisotropically etch through various layers ofa small diameter gate stack. After forming the gate stack, the sourceand drain are ion implanted. The extra capacitance generated when theimplants overlap the source and drain, acts to slow down thetransistors. Thus the width of the gate should match, not overlap, thesource and drain implants.

[0003] 100 Nanometer (hereinafter nm) gate lines in CMOS transistorsoperating at 1.2-1.5V have been described. These transistors have highdrive current, reporting a 10% improvement over existing technologies,with no change in the gate oxide thickness. In part, a notchedpolysilicon process is used to reduce the apparent gate polysilicondimension by introducing a notch at the polysilicon-gate oxideinterface. This notch enables a reduction in the total gate capacitanceby reducing the gate length dimensions at the interface to 100 nm.

[0004] Germanium devices are faster than silicon devices because themobility of their electrons is greater, and there are more of them. Thustransistors made using a silicon-germanium gate stack are of presentinterest.

[0005] It would be advantageous to reduce the effective gate width oftransistor gates including a layer of germanium by forming a notch atthe interface between a silicon layer and a germanium layer of a gatestack. In addition, a notch at the bottom of the gate would reduce thecooling capacity.

SUMMARY OF THE INVENTION

[0006] The present invention method forms a notch at thesilicon-germanium interface of a gate stack that creates a very smallapparent linewidth and preserves fast speeds for these transistors. Themethod comprises etching a multilayer gate stack in a single chamber,and over-etching the stack, forming a notch at the silicon-germaniuminterface. This over-etch step in effect narrows the width of the line,and eliminates some of the capacitance generated at the edge of the linewhere it overlaps the source and drain of the transistor.

BRIEF DESCRIPTION OF THE DRAWING

[0007]FIG. 1A illustrates a film stack to be processed in accordancewith the present invention.

[0008]FIG. 1B illustrates a film stack after processing in accordancewith the present invention wherein a notch is formed at the germaniumlayer.

[0009]FIG. 2 is a cross sectional view of a chamber suitable forcarrying out a sequence of etch steps in the chamber.

[0010]FIG. 3 is a graph of an emission endpoint taken at 3040 angstromsat the silicon-germanium interface.

[0011]FIG. 4A illustrates openings etched in accordance with theinvention taken at the center of the substrate.

[0012]FIG. 4B illustrates openings etched in accordance with theinvention taken at the edge of the substrate.

[0013]FIGS. 5A, 5B and 5C illustrate openings made by varying the amountof fluorocarbon present in the etch gas.

[0014]FIG. 6 illustrates an opening made using a wet etch treatment.

DETAILED DESCRIPTION OF THE INVENTION

[0015] A typical gate stack for processing herein is shown in FIG. 1. Acrystalline silicon substrate 10 has sequentially deposited thereover alayer of gate oxide 12 about 50 angstroms thick; a layer of amorphousgermanium 14 about 600 angstroms thick; a layer of amorphous silicon 16about 1400 angstroms thick; a layer of PECVD silicon oxide 18 about 800angstroms thick; and a bottom antireflection layer 20 about 1140angstroms thick. A patterned layer of a deep ultraviolet photoresist 22about 8000 angstroms thick is deposited and patterned to a cross sectionof about 0.18 micron in diameter.

[0016] A suitable chamber for etching through all of the above filmlayers sequentially is shown in FIG. 2. This chamber is referred to as adecoupled plasma source (DPS) chamber.

[0017] Ths inductively coupled RF plasma reactor includes a reactorchamber 100 having a grounded conductive cylindrical sidewall 110 and adielectric ceiling 112, e.g., flat or dome-like. The reactor includes asubstrate support electrode 114 for supporting a substrate 116 to beprocessed in the chamber 100; a cylindrical inductor coil 118surrounding an upper portion of the chamber beginning near the plane ofthe top of the substrate 116 or substrate support electrode 114 andextending upwardly therefrom toward the top of the chamber 100; aprocess gas source 122 and a gas inlet 124, which can be a plurality ofinlets spaced about the interior of the chamber 100; and a pump 126 forcontrolling the chamber pressure. The coil inductor 118 is energized bya plasma source power supply, or RF generator 128, through aconventional active RF match network 130, the top winding of theinductor coil 118 being “hot” and the bottom winding being grounded.Alternatively, a flat coil can be used. The substrate support electrode114 includes an interior conductive portion 132 connected to a bias RFpower supply or generator 134, and an exterior grounded conductor 136which is insulated from the interior conductive portion 132. Aconductive grounded RF shield 120 surrounds the coil inductor 118.

[0018] To carry out the present process, the source power is turned onand a fluorocarbon or hydrofluorocarbon processing gas is passed intothe chamber 100 from the desired gas containers (not shown). Thefluorocarbon gas deposits a polymer onto the photoresist layer toprotect it during the multiple etch steps to follow.

[0019] The power to the chamber 100 from the inductive RF power source128 is suitably from about 200 up to about 3000 watts, and is preferablyfrom about 500 to 2000 watts. The RF source can be a 12.56 MHz powersource. No bias power is used during the deposition step. The pressurein the chamber during this step is maintained at about 40 millitorr.

[0020] Suitable fluorocarbon gases include polymer-generating gases suchas CHF₃; C₂F₆; C₄F₆; C₄F₈; C₅F₈ and the like. Such gases form afluorocarbon, polytetrafluorethylene-like coating on the photoresist,protecting the photoresist during the subsequent etch steps. Thedeposition step is generally carried out for about five seconds.

[0021] During the etch steps, the various layers are etched as describedfurther hereinbelow.

[0022] The bottom antireflection layer is etched using hydrogen bromide,oxygen and an argon carrier gas at low pressure, comparatively lowsource power and comparatively high bias power. This etch is monitoredusing a known optical laser endpoint detection system.

[0023] The PECVD silicon oxide layer is etched using argon, oxygen and afluorocarbon, at somewhat higher pressure and bias power. This endpointis monitored using a suitable endpoint detector.

[0024] The amorphous silicon layer is etched using a mixture of hydrogenbromide and oxygen, at somewhat higher pressure and source power butsomewhat lower bias power. This endpoint is monitored using a suitableendpoint detection system.

[0025] The germanium layer is etched using the same etchant gases as foramorphous silicon, but at higher pressure, higher source power andhigher bias power.

[0026] Thus all of the layers can be etched in the same chamber simplyby changing the etch gas mixtures and the power and pressure in thechamber.

[0027] The substrate can be cooled during etch processing, generally bymeans of a coolant passed to a channel in the substrate supportelectrode 114 (not shown). In addition, a flow of a coolant gas, such ashelium, can be passed between the substrate 116 and the substratesupport 114 to enhance cooling and maintain the temperature of thesubstrate within the desired range, generally from about 10 to about100° C.

[0028] After completing the etch, a resist removal step is used to stripthe remaining resist and to notch the gate structure.

[0029] The present method is further explained in the followingExamples. However, the invention is not meant to be limited by thedetails described therein.

EXAMPLE 1

[0030] After patterning the photoresist layer as shown in FIG. 1, thevarious layers are etched as follows:

[0031] The bottom antireflection coating (BARC) layer is etched usingHBr, argon, and oxygen in a gas flow ratio of about 4:2:1. The chamberpressure was maintained at 4 millitorr, the source power was 500 watts,the bias power was 120 watts. The cathode temperature was kept at 50° C.with a backside pressure of helium of 8 torr for all of the etch steps.The wavelength monitored by the endpoint detector was 4705 angstroms.

[0032] The silicon oxide layer was etched using argon, carbontetrafluoride and oxygen at a gas flow ratio of about 30:20:1 at achamber pressure of 5 millitorr. The source power was 500 watts and thebias power was 135 watts. The etch endpoint was monitored using awavelength of 2880 angstroms.

[0033] The amorphous silicon layer was then etched with HBr and oxygenat a gas flow ratio of 60:1 and a pressure of 6 millitorr. The sourcepower used was 700 watts, the bias power 60 watts. The etch wasmonitored using a detection wavelength of 3040 angstroms. FIG. 3illustrates the emission endpoint for the silicon-germanium interface.The etch was stopped at the endpoint, permitting a repeatable softlanding for this etch.

[0034] The germanium layer was etched using the same etch gases, butincreasing the pressure to 55 millitorr, the source power to 950 wattsand reducing the bias power to 70 watts. This etch was carried out for30 seconds.

[0035] The resultant etched profiles are shown in FIGS. 4A and 4B forthe center of the wafer. FIGS. 4C and 4D show the etched profiles at theedge of the wafer. Very little notching is apparent.

[0036] The main etch is stopped after etching the silicon and germaniumlayers, but before reaching the thin gate oxide layer. In order toachieve a “soft landing”, the main etch is terminated before reachingthe thin gate oxide layer. An over-etch is carried out to remove theremaining germanium under the following conditions: gas flows of HBr andoxygen at a gas flow ratio of 60:1 and optional carbon tetrafluoride.The pressure was 55 millitorr, the source power was 950 watts, and thebias power was 70 watts, for 60 seconds.

[0037]FIG. 5A illustrates the profile obtained when no carbontetrafluoride was added. FIG. 5B illustrates the profile obtained whencarbon tetrafluoride was added to the etchant gases at a gas flow ratioof 60:1:0.5. FIG. 5C illustrates the profile obtained when carbontatrafluoride was added to the etchant gases at a gas flow rate of60:1:1. It is apparent that adding increasing amounts of carbontetrafluoride increases notching at the silicon-germanium interface toprovide a controllable etch.

EXAMPLE 2

[0038] After etching openings in the various layers as in FIG. 1, thesilicon wafer was dipped in a cleaning solution for 10 minutes. Theresultant overetch is shown in FIG. 6. It can be seen that the notch wasopened almost through the width of the line and is difficult to control.

[0039] After completing the etch, a photoresist removal step was used tostrip the remaining resist and to notch the gate structure.

[0040] The strip/notch step can also be carried out using ahydrofluorocarbon in place of, or in addition to, the fluorocarbontogether with oxygen, or by using chlorine and oxygen, or using amixture of chlorine, hydrogen bromide and oxygen.

[0041] Isotropic plasma etch stripping is shown to be more controllableas a post etch treatment than wet etching to recess the germanium layerat the germanium-oxide interface and reduce l_(eff). Depending on theetch time and the amount of fluorocarbon employed, a very controllableover-etch step can produce line widths at the silicon-germaniuminterface that are very small. However, the overall width of the line isnot affected very much, and thus the conductivity of the gate line ispreserved.

[0042] Any etchant that includes water also works very well. Liquidwater, water vapor, or a water plasma can be employed. The latter methodis preferred because it can be readily controlled. If the over-etch iscontinued too far, the germanium layer will be etched through, therebyremoving the gates.

[0043] Thus the over-etch step to form a notch at the silicon-germaniuminterface can be carried out by dipping in liquid water for about oneminute; by exposing it to water vapor, or by using an oxygen-containingplasma.

[0044] When making transistors, notching reduces the capacitance whichdevelops after ion implantation and drive-in of the source and drain,which in turn slows down the transistor speeds. To further improvetransistor speed, the ion implants should be made as close as possibleto the germanium layer.

[0045] Although the invention has been described in terms of specificembodiments, other etchants, reaction conditions, etch chambers andlayers can be substituted as will be known to one skilled in the art.These substitutions are meant to be included within the scope of theinvention, which is only to be limited by the scope of the appendedclaims.

We claim.
 1. In an etch process for etching a silicon layer over agermanium layer, the improvement comprising carrying out an over-etchusing an etchant to etch a notch at the silicon-germanium interface. 2.An etch process according to claim 1 wherein the etchant is a mixture ofhydrogen bromide and oxygen.
 3. An etch process according to claim 2wherein a fluorocarbon is added to the etchant.
 4. A method of formingtransistor gates having effective linewidths of 100 nm or less from agate stack comprising a germanium layer, an amorphous silicon layer anda plasma enhanced chemical vapor deposited silicon oxide layer over agate oxide layer comprising etching through the plasma enhanced chemicalvapor deposited silicon oxide layer, the amorphous silicon layer and thegermanium layer, and over-etching using an etchant for germanium to forma notch at the silicon-germanium interface.
 5. A method according toclaim 4 wherein the etch steps are carried out sequentially in a singleetch chamber.
 6. A method according to claim 4 wherein the etchant is amixture of hydrogen bromide, oxygen and a fluorocarbon.
 7. A methodaccording to claim 4 wherein the etchant includes a hydrofluorocarbonand oxygen.
 8. A method according to claim 4 wherein the etchantincludes chlorine and oxygen.
 9. A method according to claim 4 whereinthe etchant includes chlorine, hydrogen bromide and oxygen.
 10. A methodaccording to claim 4 wherein the etchant includes water.